PRINCIPAL SoC INTEGRATION & MID-END DESIGN SPECIALIST

⚡ HIRING: PRINCIPAL SoC INTEGRATION & MID-END DESIGN SPECIALIST ⚡

Are you a Senior Silicon Architect who commands the crucial sweet spot between pure RTL design and physical implementation We are looking for an elite Principal SoC Integration & Mid-End Design Engineer to spearhead structural signoff and timing convergence for complex, large-scale chip designs!

This is a structural, mid-end ownership seat . We are not looking for pure front-end RTL writers or back-end layout engineers—we need a powerhouse who can architect full-chip integration, own synthesis pipelines, validate advanced low-power specifications ($UPF$), and guarantee timing closure ($SDC/STA$).

Role Overview:

• Position: Principal / Lead SoC Integration Engineer (Mid-End Specialist)
• Experience Baseline: 8+ Years of deep semiconductor industry experience
• Tape-Out Proof: Must have successful, tape-out proven ASIC silicon track records
• Core Toolkit Presence: Synopsys / Cadence mid-end flows (DC, PrimeTime, Formality, Genus, Spyglass, VCLP)
• Language/Comms: Fluent English is mandatory; Mandarin speaking capability is a huge asset.
• Location: Kuala Lumpur, Malaysia / Regional Tech Hub (Permanent Placement)

️ Your Core Structural Mandate:

• SoC Integration & Fabric Assembly: Lead full-chip and subsystem-level architectural integration, merging complex functional IP modules into uniform, optimized top-level designs.
• Synthesis & Netlist Governance: Drive complex chip-level synthesis runs and conduct rigorous netlist QA to construct pristine structural primitives before back-end handoff.
• Timing Closure Hegemony ($SDC/STA$): Architect, validate, and audit multi-mode multi-corner $SDC$ constraints at both the module and Top-level layout tiers to declare safe Timing Signoff.
• Low-Power Verification ($UPF/VCLP$): Formulate low-power architecture matrices, authoring Unified Power Format (UPF) scripts, and validating multi-voltage domains with VCLP.
• Front-End Quality Gates: Run exhaustive static checks—including Clock Domain Crossing (CDC) boundaries and advanced structural Lint rules—to clean code architecture early.
• PPA Optimization & Handoff: Collaborate closely with physical design teams to optimize PPA metrics and navigate high-speed protocol blocks ( DDR, SerDes, PCIe ).

How to Apply:

If you match the 8+ years mid-end criteria and have hands-on synthesis/STA tape-out experience, send your comprehensive technical resume to:

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