...methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.
Experience in logic simulation EDA tools e.g.: Cadence Xcelium, Synopsys VCS or Mentor Questa.
Familiarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.
Programming skills (e.g....
...methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.
Advance user of logic simulation EDA tools e.g.: Cadence Xcelium, Synopsys VCS or Mentor Questa.
Experience in working closely with Design Verification team on testplan, assertions coding, functional and code...
...Knowledge in ASIC/FPGA/SoC verification or development cycle
Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
Strong communication, analytical and documentation...